Many integrated circuit devices include digital circuitry formed of metal-oxide-semiconductor (MOS) transistor devices, which are built using complementary MOS (CMOS) fabrication processes optimized for high-density, high-speed N-channel and P-channel MOS transistors. Such high-density circuitry is common in modern consumer electronic products such as wireless communications devices, portable computers, etc., in which digital circuitry is powered by batteries. In such products, it is desirable to provide a maximum amount of functionality in a limited amount of space, while keeping power consumption and cost to a minimum. To optimize circuit functionality, area, and power consumption, transistor sizes are often minimized and the transistors are designed to operate at low voltage levels. In addition, the use of simple fabrication processes aids in keeping product manufacturing costs to a minimum, wherein it is desirable to fabricate both low voltage and higher voltage transistors in an integrated circuit (IC) using a single streamlined fabrication process flow.
In fabricating integrated circuits for such battery powered products, a certain number of transistors are needed for switching power from the battery. These power transistors may need to withstand higher voltages than do the logic transistors of the IC. For example, logic transistors may be operated at voltages of about 1.8 volts or less, whereas battery power transistors may be used to switch power from batteries at 6 volts or higher. Such power switching circuits are often fabricated using N or P channel drain-extended metal-oxide-semiconductor (DEMOS) transistor devices, such as lateral diffused MOS (LDMOS) devices or REduced SURface Field (RESURF) transistors. DEMOS devices advantageously combine short-channel operation with high current handling capabilities, relatively low drain-to-source on-state resistance (Rdson), and the ability to withstand relatively high drain-to-source voltages without suffering voltage breakdown failure, where DEMOS device designs often involve a tradeoff between breakdown voltage (BVdss) and Rdson. In addition to performance advantages, DEMOS device fabrication is relatively easy to integrate into CMOS process flows, facilitating use in devices where logic, low power analog, or other circuitry is also to be fabricated in a single integrated circuit (IC).
Fabrication of semiconductor products typically involves a large number of processing steps, many of which employ masks for selectively operating on specific portions of a semiconductor wafer. Manufacturing cost for integrated circuits is a function of the number of processing steps in a given process flow, wherein reducing the number of masks and processing steps reduces the manufacturing cost. In attempting to fabricate both low voltage logic transistors and higher voltage DEMOS transistors using a streamlined fabrication process flow, the use of a single transistor gate dielectric or gate oxide is desired, in order to minimize the number of masks in the process.
In order to maintain the optimized performance of the high-speed performance of the logic transistors, moreover, thin gate dielectrics are desirable. However, the thin gate dielectric is prone to degradation from channel hot carriers and direct tunneling currents where high electric fields are present in the underlying semiconductor material. In power transistors used to switch battery power, the use of such thin gate dielectrics often results in reliability problems, wherein the spacing of the drain away from the gate may not be adequate to prevent high electric fields near the thin gate dielectric. Accordingly, there is a need for improved DEMOS transistors and fabrication methods by which streamlined fabrication processes can be used to create both low voltage logic and DEMOS transistors, while mitigating or avoiding degradation of the DEMOS transistors in semiconductor products.